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| ? semiconductor components industries, llc, 2013 february, 2013 ? rev. 0 1 publication order number: tcc ? 103/d tcc-103 ptic control ic introduction on semiconductor?s ptic controller ic is a three-output high voltage digital to analog control ic specifically designed to control and bias on semiconductor?s passive tunable integrated circuits (ptics). these tunable capacitive circuits are intended for use in mobile phones and dedicated rf tuning applications. the implementation of on semiconductor?s tunable circuits in mobile phones enables significant improvement in terms of antenna radiated performance. the tunable capacitors are controlled through a bias voltage ranging from 2 v to 20 v. the tcc ? 103 high-voltage ptic control ic has been specifically designed to c over this need, providing three independent high-voltage outputs that control up to three different tunable ptics in parallel. the device is fully controlled through a multi-protocol digital interface. features ? controls on semiconductor?s ptic tunable capacitors and rf tuners ? compliant with timing needs of cellular and other wireless system requirements ? integrated boost converter with 3 programmable outputs (up to 24 v) ? low power consumption ? auto-detection of spi (30- or 32-bit) or mipi rffe interfaces (1.2 v or 1.8 v) ? available in wlcsp (ball and peripheral arrays) and for stand-alone or module integration typical applications ? multi-band, multi-standard, advanced and simple mobile phones ? tunable antenna matching networks ? compatible with closed loop and open-loop antenna tuner applications http://onsemi.com peripheral bump case tbd see detailed ordering and shipping information in the package dimensions section on page 29 of this data sheet. ordering information marking diagrams rdl ball array case tbd tcc = product code x = mipi id a = assembly location l = wafer lot code y = year code w = week code o = pin 1 marker peripheral bump rdl tccx alyw tccx alyw tcc = product code x = mipi id a = assembly location l = wafer lot code y = year code w = week code o = pin 1 marker
tcc ? 103 http://onsemi.com 2 l_boost vhv vreg gnd_boost cs clk data atest otp level shifter interface registers start reference vio por booster regulator bandgap 4 bit dac 7 bit dac 7 bit dac 7 bit dac vreg por rc osc out a out b out c trig gndio vio gnda vdda por_vreg 7 7 7 bias_start/vreg_start vio_oi vio vdda vreg vhv figure 1. hvdac functional block diagram tcc ? 103 http://onsemi.com 3 peripheral bump pin out table 1. pin function descriptions bump name type description 1 l_boost analog hv output boost inductor 2 avdd power analog supply 3 gnd_ref power analog ground 4 trig digital i/o trigger signal input 5 cs digital input spi_cs (ground for mipi rffe) 6 clk digital input rffe sclk/spi clk 7 data digital i/o rffe sdata/spi_data 8 vio power io reference supply 9 gnd_dig power digital ground 10 outa analog hv output high voltage output a 11 outb analog hv output high voltage output b 12 outc analog hv output high voltage output c 13 vreg analog output vreg capacitor 14 atest analog output test pin (ground in application) 15 gnd_boost power boost ground 16 vhv analog hv i/o boost high voltage output peripheral bump package footprint figure 2. peripheral row footprint ? top view 1850 m 10 m 2050 m 10 m tccx 7lyw 123 4 12 11 10 9 16 15 14 13 5 6 7 8 tcc ? 103 http://onsemi.com 4 rdl pin out table 2. pin function descriptions bump name type description a1 vreg analog output vreg capacitor a2 atest analog output test pin (ground in application) a3 gnd_boost power boost ground a4 vhv analog hv i/o boost high voltage output b1 outb analog hv output high voltage output b b2 outc analog hv output high voltage output c b3 avdd power analog supply b4 l_boost analog hv output boost inductor c1 outa analog hv output high voltage output a c2 gnd_dig power digital ground c3 trig digital i/o trigger signal input c4 gnd_ref power analog ground d1 vio power io reference supply d2 data digital i/o rffe sdata/spi_data d3 clk digital input rffe sclk/spi clk d4 cs digital input spi_cs (ground for mipi rffe) rdl ball array package footprint figure 3. ball array footprint ? top view 2050 m 10 m 1850 m 10 m tccx 7lyw a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 tcc ? 103 http://onsemi.com 5 electrical performance specifications table 3. absolute maximum ratings symbol parameter rating unit avdd analog supply voltage ? 0.3 to +6.0 v vio io reference supply voltage ? 0.3 to +3.6 v v i/o input voltage logic lines (data, clk, cs) ? 0.3 to vio v vhv vhv maximum voltage ? 0.3 to 30 v v esd (hbm) human body model, jesd22-a114, all i/o 2,000 v v esd (mm) machine model, jesd22-a115 200 v t stg storage temperature ? 55 to +150 c t amb_op_max max operating ambient temperature without damage +110 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 4. recommended operating conditions symbol parameter rating unit min typ max t amb_op operating ambient temperature ? 30 ? +85 c t j_op operating junction temperature ? 30 ? +125 c avdd analog supply voltage 2.3 ? 5.5 v vio io reference supply voltage 1.1 ? 3.0 v table 5. dc characteristics (t a = ? 30 to +85 c; v outx = 15 v for each output; 2.3 v < avdd < 5.5 v; 1.1 v < vio < 3.0 v; r load = equivalent series load of 5.6 k and 2.7 nf; c hv = 22 nf; l boost =15 h; trig pin grounded; unless otherwise specified) symbol parameter min typ max unit comment shutdown mode i avdd avdd supply current ? ? 0.8 a vio supply is low i l_boost l_boost leakage ? ? 1 a vio supply is low i batt battery current ? ? 1 a vio supply is low i vio vio supply current ? 1 ? 1 a vio supply is low i clk clk leakage ? 1 ? 1 a vio supply is low i data data leakage ? 1 ? 1 a vio supply is low active mode i batt average battery current, 3 outputs actively switching 16 v for 1205 s to 2 v for 1705 s to 8v for 1705 s ? 980 1,290 a at vhv = 20 v avdd = 3.3 v i batt_ss0 average battery current, 3 outputs @ 0 v steady state ? 590 830 a at vhv = 20 v avdd = 3.3 v i batt_ss2 average battery surrent, 3 outputs @ 2 v steady state ? 610 860 a at vhv = 20 v avdd = 3.3 v i batt_ss16 average battery current, 3 outputs @ 20 v steady state ? 780 1,020 a at vhv = 20 v avdd = 3.3 v i l_boost average inductor current, 3 outputs actively switching 20 v for 1205 s to 2 v for 1705 s to 8 v for 1705 s ? 730 1,000 a at vhv = 20 v avdd = 3.3 v i l_boost_ss0 average inductor current, 3 outputs @ 0 v steady state ? 350 550 a at vhv = 20 v avdd = 3.3 v i l_boost_ss2 average inductor current, 3 outputs @ 2 v steady state ? 380 570 a at vhv = 20 v avdd = 3.3 v tcc ? 103 http://onsemi.com 6 table 5. dc characteristics (continued) (t a = ? 30 to +85 c; v outx = 15 v for each output; 2.3 v < avdd < 5.5 v; 1.1 v < vio < 3.0 v; r load = equivalent series load of 5.6 k and 2.7 nf; c hv = 22 nf; l boost =15 h; trig pin grounded; unless otherwise specified) symbol comment unit max typ min parameter active mode (continued) i l_boost_ss16 average inductor current, 3 outputs @ 20 v steady state ? 550 750 a at vhv = 20 v avdd = 3.3 v i vio_inact vio average inactive current ? ? 3 a vio is high, no bus activity i vio_active vio average active current ? ? 250 a vio = 1.8 v, master sending data at 26 mhz v vreg 2.05 ? 2.3 v no external load allowed low power mode i avdd avdd supply current ? ? 7 a i l_boost l_boost leakage ? ? 3 a i batt battery current ? ? 10 a i avdd + i l_boost i vio vio supply current ? ? 3 a no bus activity v vreg 2.0 ? 3.3 v no external load allowed table 6. boost converter characteristics (avdd from 2.3 v to 5.5 v; vio from 1.1 v to 3.0 v; t a = ?30 to +85 c; c hv = 22 nf; l boost =15 h; unless otherwise specified) symbol parameter conditions min typ max unit vhv_min minimum programmable output voltage (average), dac boost = 0h active mode 8.5 9 9.5 v vhv_max maximum programmable output voltage (average), dac boost = fh active mode 22.8 24 25.2 v resolution boost voltage resolution 4 bit dac ? 1 ? v r ds(on) n-channel mosfet on-resistance i l_boost = 10 ma ? 1.3 ? i l_boost_limit inductor current limit ? 100 ? ma tcc ? 103 http://onsemi.com 7 table 7. analog outputs (out a, out b, out c) (avdd from 2.3 v to 5.5 v; vio from 1.1 v to 3.0 v; vhv = 24 v; t a = ? 30 to +85 c; r load = unless otherwise specified) parameter description min typ max unit comment shutdown mode z out out a, out b, out c output impedance 7 ? ? m dac disabled active mode v oh maximum output voltage 22.0 ? ? v dac a, b or c = ffh, dac boost = fh, i oh <10 a v ol minimum output voltage ? ? 1 v dac a, b or c = 01h, dac boost = 0h to fh, i oh <10 a slew rate ? 6.5 10 s 2 v to 20 v step, measured at v out = 15.2 v, r load = equivalent series load of 5.6 k and 2.7 nf, turbo enabled r pd out a, out b, out c set in pull down mode ? ? 800 dac a, b or c = 00h, dac boost = 0h to fh, selected output(s) is disabled resolution voltage resolution (1 bit) ? 188 ? mv (1 lsb = 1 bit) v offset zero scale, least squared best fit -1 ? +1 lsb error -3.0 ? +3.0 %v out over 2 v ? 18 v v o range dnl differential non-linearity least squared best fit -0.9 ? +0.9 lsb over 2 v ? 18 v v o range inl integral non-linearity least squared best fit -1 ? +1 lsb over 2 v ? 18 v v o range i sc over current protection ? 35 65 ma any dac output to ground v ripple output ripple with all outputs at steady state ? ? 10 mv rms over 2 v ? 18 v v o range, vhv = 20 v tcc ? 103 http://onsemi.com 8 theory of operation overview the control ic outputs are directly controlled by programming the three dacs (dac a, dac b, and dac c) through the digital interface. the dacs are 8-bit dacs used in a 7-bit format. the dac stages are driven from a reference voltage, generating an analog output voltage driving a high-voltage amplifier supplied from the boost converter (see control ic block diagram ? figure 1). the control ic output voltages are scaled from 0 to 24 v, with 128 steps of 188 mv (2 24 v/255 = 0.188235 v). the nominal control ic output can be approximated to 188 mv (dac value). for performance optimization the boost output voltage (vhv) can be programmed to levels between 9 v and 24 v via the dac_boost register (4 bits with 1 v steps). the startup default level for the boosted voltage is vhv = 20 v. for proper operation and to avoid saturation of the output devices and noise issues it is recommended to operate the boosted vhv voltage at least 2 v above the highest programmed v out voltage of any of the three outputs. when the dac output value is set to 00h the corresponding output is disabled and the output is pulled to gnd through an effective impedance of less than 800 . operating modes the following operating modes are available: 1. shutdown mode: all circuit blocks are off, the dac outputs are disabled and placed in high z state and current consumption is limited to minimal leakage current. the shutdown mode is entered upon initial application of avdd or upon vio being placed in the low state. the contents of the registers are not maintained in shutdown mode. 2. startup mode: startup is only a transitory mode. startup mode is entered upon a vio high state. in startup mode all registers are reset to their default states, the digital interface is functional, the boost converter is activated, outputs out a, out b, and out c are disabled and the dac outputs are placed in a high z state. control software can request a full hardware and register reset of the tcc ? 103 by sending an appropriate pwr_mode command to direct the chip from either the active mode or the low power mode to the startup mode. from the startup mode the device automatically proceeds to the active mode. 3. active mode: all blocks of the tcc ? 103 are activated and the dac outputs are fully controlled through the digital interface. the dac settings can be dynamically modified and the hv outputs will be adjusted according to the specified timing diagrams. each dac can be individually controlled and/or switched off according to application requirements. active mode is automatically entered from the startup mode. active mode can also be entered from the low power mode under control software command. 4. low power mode : in low power mode the serial interface is enabled, the dac outputs are disabled and are placed in a high z state and the boost voltage circuit is disabled. control software can request to enter the low power mode from the active mode by sending an appropriate pwr_mode command. the contents of all registers are maintained in the low power mode. avdd power-on reset upon application of avdd the tcc ? 103 will be in shutdown mode. all circuit blocks are off and the chip draws only minimal leakage current. vio power-on reset and startup conditions a high level on vio places the chip in startup mode which provides a power on reset (por) to the tcc ? 103. por resets all registers to their default settings as described in table 8. vio por also resets the serial interface circuitry. por is not a brown-out detector and vio needs to be brought back to a low level to enable the por to trigger again. table 8. vio power-on reset and startup register default state for vio por comment dac boost [1011] vhv = 20 v power mode [01] > [00] transitions from shutdown to startup and then automatically to active mode dac enable [000] v out a, b and c disabled dac a output in high-z mode dac b output in high-z mode dac c output in high-z mode vio shutdown a low level at any time on vio places the chip in shutdown mode in which all circuit blocks are off. the contents of the registers are not maintained in shutdown mode. tcc ? 103 http://onsemi.com 9 table 9. vio thresholds (avdd from 2.3 v to 5.5 v; t a = ?30 to +85 c unless otherwise specified) parameter description min typ max unit comment viorst vio low threshold ? ? 0.2 v when vio is lowered below this threshold level the chip is reset and placed into the shutdown state. power supply sequencing the avdd input is typically directly supplied from the battery and thus is the first on. after avdd is applied and before vio is applied to the chip all circuits are in the shutdown state and draw minimum leakage currents. upon application of vio the chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface. table 10. timing (avdd from 2.3 v to 5.5 v; vio from 1.1 v to 3.0 v; t a = ?30 to +85 c; out a, out b & out c; chv = 22 nf; l boost =15 h; vhv = 20 v; turbo-charge mode off unless otherwise specified) parameter description min typ max unit comment t por_vreg internal bias settling time from shutdown to active mode ? 50 120 s for info only t boost_start time to charge chv @ 95% of set vhv ? 130 ? s for info only t sd_to_act startup time from shutdown to active mode ? 180 250 s t set+ output a, b, c positive settling time to within 5% of the delta voltage, equivalent series load of 5.6 k and 2.7 nf, v out from 2 v to 20 v; 0bh (11d) to 55h (85d) ? 50 60 s voltage settling time connected on v out a, b, c t set ? output a, b, c negative settling time to within 5% of the delta voltage, equivalent series load of 5.6 k and 2.7 nf, v out from 20 v to 2 v; 55h (85d) to 0bh (11d) ? 50 60 s voltage cettling time connected on v out a, b, c figure 4. output setting diagram tcc ? 103 http://onsemi.com 10 figure 5. startup timing diagram tcc ? 103 http://onsemi.com 11 boost control the tcc ? 103 integrates an asynchronous current control boost converter. it operates in a discontinuous mode and features spread-spectrum circuitry for electro-magnetic interference (emi) reduction. the average boost clock is 2 mhz and the clock is spread between 0.8 mhz and 3.2 mhz. boost output voltage (vhv) control principle the asynchronous control starts the boost converter as soon as the vhv voltage drops below the reference set by the 4-bit dac and stops the boost converter when the vhv voltage rises above the reference again. due to the slow response time of the control loop, the vhv voltage may drop below the set voltage before the control loop compensates for it. in the same manner, vhv can rise higher than the set value. this effect may reduce the maximum output voltage available. please refer to figure 6 below. the asynchronous control reduces switching losses and improves the output (vhv) regulation of the dc/dc converter under light load, particularly in the situation where the tcc ? 103 only maintains the output voltages to fixed values. figure 6. vhv voltage waveform boost running chv recharge chv discharge time delay delay delay vhv set vhv high impedance (high z) feature in shutdown mode the out pins are set to a high impedance mode (high z). following is the principle of operation for the control ic: 1. the output voltage v out is defined by: v out dac code 255 24 v 2 (eq. 1) 2. the voltage vhv defines the maximum supply voltage of the output regulator and is set by the 4 bit dac. 3. the maximum dc output voltage v out is limited to (vhv ? 2 v). 4. the minimum output voltage v out is 1.0 v max. figure 7. dac output range example a figure 8. dac output range example b tcc ? 103 http://onsemi.com 12 digital interface the control ic is fully controlled through a digital interface (data, clk, cs). the digital interface automatically detects and responds to mipi rffe interface commands, 3-wire 30-bit serial interface commands or 3-wire 32-bit serial interface commands. auto-detection is accomplished on a frame by frame basis. the digital interface is further described in the next sections of this document. 3-wire serial interface the 3-wire serial interface operates in a synchronous write-only 3-wire slave mode. 30-bit or 32-bit message length is automatically detected for each frame. if cs changes state before all bits are received then all data bits are ignored. data is transmitted most significant bit first and data is latched on the rising edge of clk. commands are latched on the falling edge of cs. table 11. 3-wire serial interface specification (t a = ? 30 to +85 c; 2.3 v < avdd < 5.5 v; 1.1 v < vio < 3.0 v; unless otherwise specified) parameter description min typ max unit comment f clk clock frequency ? ? 26 mhz t clk clock period 38.4 ? ? ns n bit bits number ? 30/32 ? bits auto-detection 30-bit or 32-bit t high clock high time 13 ? ? ns t low clock low time 13 ? ? ns tcs setup cs set-up time 5 ? ? ns 70% rising edge of cs to 30% rising edge of first clock cycle tcs hold cs hold time 5 ? ? ns 30% falling edge of last clock cycle to 70% falling edge of cs td setup data set-up time 4 ? ? ns relative to 30% of clk rising edge td hold data hold time 4 ? ? ns relative to 70% of clk rising edge t succ cs low time between successive writes 38.4 ? ? ns 70% falling edge of cs to 70% rising edge of cs t succ cs low time between successive dac update writes 1,500 ? ? ns time between groups of dac update reg [00000] & [00001] writes c clk input capacitance ? ? 5 pf clk pin c data input capacitance ? ? 8.3 pf data pin c cs input capacitance ? ? 5 pf cs pin c trig input capacitance ? ? 10 pf trig pin v ih input logic level high 0.7 vio ? vio + 0.3 v data, clk, cs v il input logic level low ? 0.3 ? 0.3 vio v data, clk, cs i ih_data input current high ? 2 ? 10 a data i il_data input current low ? 2 ? 1 a data i ih_clk,cs input current high ? 1 ? 10 a clk, cs i il_clk,cs input current low ? 1 ? 1 a clk, cs v tp_trig positive going threshold voltage 0.4 vio ? 0.7 vio v trig v tn_trig negative going threshold voltage 0.3 vio ? 0.6 vio v trig v h_trig hysteresis voltage (v tp ? v tn ) 0.1 vio ? 0.4 vio v trig i ih_trig trig input current high ? 2 ? 10 a trig = 0.8 vio i il_trig trig input current low ? 2 ? 1 a trig = 0.2 vio tcc ? 103 http://onsemi.com 13 figure 9. 3-wire serial interface signal timing spi frame length decoding 30-bit or 32-bit frame length is automatically detected. the length of the frame is defined by the number of clock rising edges while cs is kept high. the tcc ? 103 will not respond to a spi command if the length of the frame is not exactly 30 bits or 32 bits. spi registers are write only. spi frame structure table 12. 32 bits frame: address decoding (1 or 2 or 3 outputs) h0 h1 r/w a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 0 1 0 1 0 0 1 0 0 x x x x x on semiconductor header r/w device id specific device id register address for operation table 13. 30 bits frame: address decoding (1 or 2 or 3 outputs) r/w a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 1 0 0 1 0 0 x x x x x r/w device id specific device id register address for operation table 14. 3-wire serial interface address map a4 a3 a2 a1 a0 data [15:8] data [7:0] 0 0 0 0 0 turbo charge settings for dac a, b, c dac c 0 0 0 0 1 dac b dac a 0 0 1 0 0 turbo-charge delay parameters for dac a, b, c turbo threshold delay settings for a, b, c 1 0 0 0 0 mode select + control ic setup 1 0 0 1 0 reserved reserved to 1 1 1 1 1 tcc ? 103 http://onsemi.com 14 turbo-charge mode the tcc ? 103a control ic has a t urbo-charge mode that significantly shortens the system settling time when changing programming voltages. in t urbo-charge mode the dac output target voltage is temporarily set to either a delta voltage above or a delta voltage below the actual desired target for the tcdly time. it is recommended that vhv be set to 24 v when using turbo-charge mode. table 15. data decoding for data register [00000] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 tc_indx[7:0] tc_indx[10] dac c table 16. data decoding for data register [00001] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 tc_indx[9] dac b tc_indx[8] dac a table 17. first and last 26 values of turbo time encoded table into tc_indx [10:0] register dac a state dac b state dac c state encoded value dec dec dec dec hex 0 0 0 0 0 0 0 1 1 1 0 0 2 2 2 0 0 3 3 3 0 0 4 4 4 0 0 5 5 5 0 0 6 6 6 0 0 7 7 7 0 0 8 8 8 0 0 9 9 9 0 0 10 10 a 0 0 11 11 b 0 1 0 12 c 0 1 1 13 d 0 1 2 14 e 0 1 3 15 f 0 1 4 16 10 0 1 5 17 11 0 1 6 18 12 0 1 7 19 13 0 1 8 20 14 0 1 9 21 15 0 1 10 22 16 0 1 11 23 17 0 2 0 24 18 0 2 1 25 19 last 25 values 11 9 11 1703 6a7 11 10 0 1704 6a8 11 10 1 1705 6a9 11 10 2 1706 6aa tcc ? 103 http://onsemi.com 15 table 17. first and last 26 v alues of turbo time encoded table into tc_indx [10:0] register (continued) dac a state encoded value dac c state dac b state dec hex dec dec dec 11 10 3 1707 6ab 11 10 4 1708 6ac 11 10 5 1709 6ad 11 10 6 1710 6ae 11 10 7 1711 6af 11 10 8 1712 6b0 11 10 9 1713 6b1 11 10 10 1714 6b2 11 10 11 1715 6b3 11 11 0 1716 6b4 11 11 1 1717 6b5 11 11 2 1718 6b6 11 11 3 1719 6b7 11 11 4 1720 6b8 11 11 5 1721 6b9 11 11 6 1722 6ba 11 11 7 1723 6bb 11 11 8 1724 6bc 11 11 9 1725 6bd 11 11 10 1726 6be 11 11 11 1727 6bf the turbo time is encoded into tc_indx register, using the formula: index state_a 144 state_b 12 state_c (eq. 2 ) tc_indx [10:0] register mapping: tc_indx [7:0] = spi_reg_0x00, bit [15:8] tc_indx [8] = spi_reg_0x01, bit 7 tc_indx [9] = spi_reg_0x01, bit 15 tc_indx [10] = spi_reg_0x00, bit 7 hardware extracts the state of each dac from the encoded turbo time table (table 17), and applies the corresponding delay from table 18 . table 18. tuning tcdly steps [ s] turbo steps [ s] {from table 21} dac state 0 1 2 3 4 5 6 7 8 9 10 11 5 turbo off 5 10 15 20 25 30 35 40 45 50 55 4 turbo off 4 8 12 16 20 24 28 32 36 40 44 3 turbo off 3 6 9 12 15 18 21 24 27 30 33 2 turbo off 2 4 6 8 10 12 14 16 18 20 22 the value of turbo time is deducted based on the hardware comparison of new dac value in respect to old dac value, as follows: if dac new > dac old, then t up = tcdly if dac new < dac old, and dac new > 21, then t down = tcdly if dac new < dac old, and dac new = 21, then t down = tcdly if dac new < dac old, and dac new < 21, then t down = tcdly + tcm (21 ? dac new) tcc ? 103 http://onsemi.com 16 table 19. turbo-charge delay parameters register for a, b & c [00100] d15 d14 d13 d12 d11 d10 d9 d8 reserved tcm_c_1 tcm_c_0 tcm_b_1 tcm_b_0 tcm_a_1 tcm_a_0 d7 d6 d5 d4 d3 d2 d1 d0 reserved tcstp_dac _c_1 tcstp_dac _c_0 tcstp_dac _b_1 tcstp_dac _b_0 tcstp_dac _a_1 tcstp_dac _a_0 table 20. turbo-charge multiplication settings (tcm) tcm_x_1 tcm_x_0 multiplication factor 0 0 4 (default) 0 1 3 1 0 2 1 1 1 table 21. turbo-charge delay step settings (tcstp_dac) tcstp_dac_x_1 tcstp_dac_x_0 turbo steps [ s] 0 0 2 0 1 3 1 0 4 1 1 5 (default) the process of decoding tc_indx is based on comparing the corresponding msb or lsb bits, because the index is incremental. after the dac states are extracted, the delay values are applied from table 18, as start value for a count-down timer. optional fine tuning of the turbo time, is available through register shown in table 21. configuration message (dac configuration - enable mask, hvdac boost and trigger pin settings) table 22. data decoding for data register [10000] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sse tp te 1 dac boost power mode 0 0 dac a dac b dac c x sse ? spread spectrum enable bit tp ? external trigger signal polarity bit te ? external trigger enable bit. when te is enabled sending messages to data registers 0x00000 and 0x00001 (with spi messages: 0xd4, 0x80, tcc ? 103 http://onsemi.com 17 table 24. boost dac mode setup d11 d10 d9 d8 vhv (v) 0 0 0 0 9 0 0 0 1 10 0 0 1 0 11 0 0 1 1 12 0 1 0 0 13 0 1 0 1 14 0 1 1 0 15 0 1 1 1 16 1 0 0 0 17 1 0 0 1 18 1 0 1 0 19 1 0 1 1 20 (default) 1 1 0 0 21 1 1 0 1 22 1 1 1 0 23 1 1 1 1 24 table 25. power mode setup d7 d6 state description 0 0 active boost control active, vhv set by digital interface v out a, b, c enabled and controlled by digital interface (default) 0 1 startup boost control active, vhv set by digital interface v out a, b, c disabled 1 0 low power digital interface is active and all other circuits are in low power mode 1 1 reserved state of hardware does not change trig pin operation with spi the trig input pin can be used as an external synchronization signal to ensure that new dac settings are applied to the outputs at appropriate times in an overall transceiver system. the trig trigger function is enabled or disabled by register [10000], bit d13 (te, trigger enable). the default for te is disabled. the external trig input is referenced to vio. the trig input is edge sensitive. the trig input signal width must be at least 1,500 ns, otherwise it will be ignored by the digital logic. to improve interfacing options the polarity of the trig signal is programmable via register [10000], bit d14 (tp, t rigger polarity). the default for tp is low-to-high transition of the trig signal. when the trig input pin is enabled (d13 = te set to 1 with a write to register [10000]), the requested dac voltage levels are set up in shadow registers and not transferred to the destination registers until the trigger condition is met. in this manner the change in dac output voltage levels are synchronized with the external trig event (active edge). if multiple dac voltage level requests are received before the trig event occurs, only the last fully received dac output voltage level will be applied to the outputs. if the external trigger function is not needed in the application, the trig pin should be grounded and the trig function disabled. when trig is disabled, the requested dac voltage levels are immediately applied to the outputs and are not synchronized with the trig signal. table 26. dac mode setup: dac enable d3 d2 d1 dac a dac b dac c 0 0 0 off off off (default)* 0 0 1 off off enabled 0 1 0 off enabled off 0 1 1 off enabled enabled 1 0 0 enabled off off 1 0 1 enabled off enabled 1 1 0 enabled enabled off 1 1 1 enabled enabled enabled *if all bits [3:1] are ?0?, then incoming dac messages will be ignored until at least one of [3:1] is set ?1?. tcc ? 103 http://onsemi.com 18 rf front-end control interface (mipi rffe interface) the tcc ? 103 is a write-only slave device which is fully compliant to the mipi alliance specification for rf front-end control interface (rffe) version 1.00.00 03 may 2010. this device is rated at full-speed operation for 1.65 v < vio < 1.95 v and at half-speed operation for 1.1 v < vio < 1.65 v. when using the mipi rffe interface the cs pin is grounded. table 27. mipi rffe interface specification (t a = ? 30 to +85 c; 2.3 v < avdd < 5.5 v; 1.1 v < vio < 1.95 v; unless otherwise specified) parameter description min typ max unit comment f sclk clock full-speed frequency 0.032 ? 26 mhz full-speed operation: 1.65 v < vio < 1.95 v t sclk clock full-speed period 0.038 ? 32 s full-speed operation: 1.65 v < vio < 1.95 v t sclkih clk input high time 11.25 ? ? ns full-speed t sclkil clk input low time 11.25 ? ? ns full-speed f sclk_half clock half-speed frequency 0.032 ? 13 mhz t sclk_half clock half-speed period 0.077 ? 32 s t sclkih clk input high time 24 ? ? ns half-speed t sclkil clk input low time 24 ? ? ns half-speed v tp positive going threshold voltage 0.4 vio ? 0.7 vio v clk, data, trig, 1.2 or 1.8 v bus v tn negative going threshold voltage 0.3 vio ? 0.6 vio v clk, data, trig, 1.2 or 1.8 v bus v h hysteresis voltage (v tp ?v tn ) 0.1 vio ? 0.4 vio v clk, data, trig, 1.2 or 1.8 v bus i ih input current high ? 2 ? +10 a trig, sdata = 0.8 vio ? 1 ? +10 a sclk = 0.8 vio i il input current low ? 2 ? +1 a trig, sdata = 0.2 vio ? 1 ? +1 a sclk = 0.2 vio c clk input capacitance ? ? 5 pf clk pin c data input capacitance ? ? 8.3 pf data pin c trig input capacitance ? ? 10 pf trig pin td setup data setup time ? ? 1 ns full-speed td hold data hold time ? ? 5 ns full-speed td setup data setup time ? ? 2 ns half-speed td hold data hold time ? ? 5 ns half-speed t succ time between successive dac update writes 1,500 ? ? ns tcc ? 103 http://onsemi.com 19 the hvdac contains twenty-four 8 bit registers. register content is described in table 35. some additional registers, implement as provision, are not described in this document. table 28. mipi rffe address map register address description purpose access type size (bits) 0x00 dac configuration (enable mask) high voltage output enable mask write 7 0x01 turbo register dac a, b & c turbo-charge configuration dac a, b & c write 8 0x02 dac a register used to set up out a write 8 0x03 dac b register used to set up out b write 8 0x04 dac c register used to set up out c write 8 0x10 dac boost (vhv) settings for the boost high voltage write 8 0x11 trigger register trigger configuration write 8 0x12 turbo-charge delay dac a, b, c turbo-charge delay steps dac a, b, c write 8 0x13 turbo-charge delay dac a, b, c turbo-charge delay multiplication dac a, b, c write 8 0x1c power mode and trigger register power mode & trigger control pwr_mode [7:6] trig_reg [5:0] write 8 0x1d product id register product number * hard coded into asic (write) 8 0x1e manufacturer id register mn (10 bits long) manufacturer id[7:0] hard coded into asic (write) 8 0x1f unique slave identifier register (usid) spare [7:6] [5,4] = manufacturer id [9:8] usid [3:0] write 8 *the two least significant bits are programmed in otp during manufacture. tcc ? 103 http://onsemi.com 20 configuration settings table 29. dac configuration (enable mask) at [0x00] bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sse 0 reserved 0 reserved dac a dac b dac c 0 reserved sse = 0 spread spectrum disabled, sse = 1 spread spectrum enabled (default) dac a, b, c = 1 when output is enabled dac a, b, c = 0 when output is off (default); if all three dac a, dac b, and dac c bits are set to ?0? then incoming dac messages will be ignored until at least one is set to ?1?. table 30. boost dac mode setup (vhv) at [0x10] (note 1) bit 7* bit 6* bit 5* bit 4 bit 3 bit 2 bit 1 bit 0 vhv (v) 0 0 0 1 0 0 0 0 9 0 0 0 1 0 0 0 1 10 0 0 0 1 0 0 1 0 11 0 0 0 1 0 0 1 1 12 0 0 0 1 0 1 0 0 13 0 0 0 1 0 1 0 1 14 0 0 0 1 0 1 1 0 15 0 0 0 1 0 1 1 1 16 0 0 0 1 1 0 0 0 17 0 0 0 1 1 0 0 1 18 0 0 0 1 1 0 1 0 19 0 0 0 1 1 0 1 1 20 (default) 0 0 0 1 1 1 0 0 21 0 0 0 1 1 1 0 1 22 0 0 0 1 1 1 1 0 23 0 0 0 1 1 1 1 1 24 1. bit 4 is fixed at logic 1 for reverse sw compatibility. *indicates reserved bits. mipi rffe trig operation the mipi rffe trigger mode can be used as a synchronization signal to ensure that new dac settings are applied to the outputs at appropriate times in the overall transceiver system. when the mipi rffe trig function is enabled via [0x11] bit 4 the requested dac voltage levels are set up in the shadow registers and not transferred to the destination registers until the trigger condition is met. in this manner the change in output voltage levels are synchronized with the mipi rffe trig command. if multiple dac voltage level requests are received before the trig event occurs, only the last fully received dac output voltage level will be applied to the outputs. the trigger configuration also provides for an additional external trig pin to be used as a synchronization signal. the external trig is independent from the built-in triggers available within the mipi rffe interface. when the trig input pin is enabled via [0x11] bit 4 the requested dac voltage levels are set up in the shadow registers and are not transferred to the destination registers until the external trigger condition is met. in this manner the change in output voltage levels are synchronized with the external trig event. the external trig input is referenced to vio. to improve interfacing options the polarity of external trig is programmable via [0x11] bit 1. if the external trigger function is not needed in the application, the trig pin should be grounded and the trig function disabled. when mipi rffe trigger and the external trig input are disabled, the requested dac voltage levels are immediately applied to the outputs and are not synchronized with the mipi rffe trigger modes or the external trig signal. tcc ? 103 http://onsemi.com 21 table 31. trigger configuration at [0x11] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved 0 reserved 0 reserved 0 trig select 0 = ext trig pin 1 = rffe trigger reserved 0 trig edge 0 = active falling 1 = active rising mask ext trig 1 = mask table 32. external trigger configuration bit settings at [0x11] bit 4 bit 3 bit 2 bit 1 bit 0 description 0 ? ? ? ? external trigger pin is enabled. sending the rffe message will load a ?shadow? registers only. only upon an active signal on external trig pin are the output registers loaded with the new voltage settings which are then applied to the outputs. 1 ? ? ? ? the mipi rffe trigger is enabled. (default) ? ? ? 0 ? external trig pin signal is active falling. ? ? ? 1 ? external trig pin signal is active rising. (default) ? ? ? ? 0 external trigger pin is not masked ? ? ? ? 1 mask external trigger pin (default) table 33. power mode and trigger register [0x1c] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pm1 pm0 trigger mask 2 trigger mask 1 trigger mask 0 trigger 2 trigger 1 trigger 0 writing a logic one (?1?) to the bits 0, 1 or 2 (t rigger 0, 1 or 2) moves data from the shadow registers into the destination registers. default for bit 0, 1 & 2 is logic low. if trigger mask 0, 1 or 2 bit is set (?1?) the t rigger 0, 1 or 2 are disabled respectively and the data goes directly to the destination register. default for bit 3, 4 & 5 is logic low. all three triggers behave in the same way as the external pin trig. when each of these triggers is set using the mipi rffe interface the results are the same as when an active edge is applied to the trig pin when external pin trig is selected. table 34. power mode bit settings in register [0x1c] pm1 pm0 state description 0 0 active boost control active, vhv set by digital interface v out a, b, c enabled and controlled by digital interface (default) 0 1 startup boost control active, vhv set by digital interface v out a, b, c disabled 1 0 low power digital interface is active while all other circuits are in low power mode 1 1 reserved state of hardware does not change table 35. product_id register at [0x1d] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1* bit 0* pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 0 0 0 0 0 1 0 0 *programmed in otp during manufacture (4 combinations of product id possible). table 36. manufacturer_id register at [0x1e] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mpn7 mpn6 mpn5 mpn4 mpn3 mpn2 mpn1 mpn0 0 0 1 0 1 1 1 0 table 37. spare(1:0), manufacturer_id(9:8), usid(3:0) register at [0x1f] bit 7 bit 6 bit 5 bit 4 bit 3* bit 2* bit 1* bit 0* reserved reserved mpn9 mpn8 usid3 usid2 usid1 usid0 0 0 0 1 0 1 1 1 *changes to the usid are not retained during shutdown power mode. tcc ? 103 http://onsemi.com 22 dac output register setting the control ic output voltages are scaled from 0 to 24 v, with 128 steps of 188 mv ((24 v/255) 2 = 0.188 v). the nominal control ic output can be approximated to 188 mv (dac value). the dac output voltage settings are stored in registers [0x02], [0x03] & [0x04] in 7-bit binary form: table 38. turbo-charge dac a, b & c register [0x01] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc_indx [7:0] table 39. dac a register [0x02] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc_indx [8] dac a value (default = 0000000) table 40. dac b register [0x03] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc_indx [9] dac b value (default = 0000000) table 41. dac c register [0x04] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc_indx [10] dac c value (default = 0000000) the turbo time is encoded into tc_indx register, using the formula: index state_a 144 state_b 12 state_c (eq. 3 ) tc_indx [10:0] register mapping: tc_indx [7:0] = rffe_reg_0x01, bit [7:0] tc_indx [8] = rffe_reg_0x02, bit 7 tc_indx [9] = rffe_reg_0x03, bit 7 tc_indx [10] = rffe_reg_0x04, bit 7 see table 17. turbo-charge mode table 42. turbo-charge delay steps [0x12] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tc_stp_ dac_c1 tc_stp_ dac_c0 tc_stp_ dac_b1 tc_stp_ dac_b0 tc_stp_ dac_a1 tc_stp_ dac_a0 note: tc_stp_dac_x is defined in the table 21. table 43. turbo-charge delay multiplication [0x13] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tcm_c1 tcm_c0 tcm_b1 tcm_b0 tcm_a1 tcm_a0 note: tcm_x is defined in the table 20 . tcc ? 103 http://onsemi.com 23 command sequences ? register 0 write (used to access the register 0 dac configuration - enable mask). register 0 can be also be accessed using register write or/and extended register write. ? register write (used to access only one register at the time) ? extended register write (used to access a group of contiguous registers with one command) register 0 write command sequence the command sequence starts with a sequence start condition (ssc) which is followed by the register 0 write command frame. this frame contains the slave address, a logic one, and the seven bit word that will be written to register 0. the command sequence is depicted below. figure 10. register 0 write command sequence table 44. mipi rffe command frame for register 0 write command sequence description ssc command frame bp sse & dac configuration 1 0 sa [3,0] 1 sse 0 0 dac_a dac_b dac_c 0 p bp register write command sequence the write register command sequence may be used to access each register (addresses 0-31). figure 11. register write command sequence table 45. mipi rffe command frame for register 0 write command sequence description ssc command frame data frame bp turbo charge settings 1 0 sa [3,0] 0 1 0 0 0 0 0 1 p turbo charge [7:0] p bp register write dac a 1 0 sa [3,0] 0 1 0 0 0 0 1 0 p tc [8] & dac_a [6:0] p bp register write dac b 1 0 sa [3,0] 0 1 0 0 0 0 1 1 p tc [9] & dac_b [6:0] p bp register write dac c 1 0 sa [3,0] 0 1 0 0 0 1 0 0 p tc [10] & dac_c [6:0] p bp tcc ? 103 http://onsemi.com 24 extended register write command sequence in order to access more than one register in one sequence this message could be used. most commonly it will be used for loading three dac registers at the same time. the four lsbs of the extended register write command frame determine the number of bytes that will be written by the command sequence. a value of 0b0000 would write one byte and a value of 0b1111 would write sixteen bytes. if more than one byte is to be written, the register address in the command sequence contains the address of the first extended register that will be written to and the slave?s local extended register address shall be automatically incremented by one for each byte written up to address 0x1f, starting from the address indicated in the address frame. figure 12. extended register write command sequence table 46. extended register write description ssc command frame address frame extended register write turbo charge & dac op code tcc ? 103 http://onsemi.com 25 figure 13. recommended mipi rffe interface application schematic tcc ? 103 http://onsemi.com 26 figure 14. recommended 3-wire serial interface application schematic table 47. recommended external bom component description nominal value package (inch) recommended p/n c boost boost supply capacitor, 10 v 1 f 0402 tdk: c1005x5r1a105k l boost boost inductor 15 h 0603 coilcraft: 0603ls-153x_l abco: lps181210t-150m others: tdk: vls2010et-150m sumida: cdh20d11dldnp-150mc r filt decoupling resistor, 5% 3.3 0402 vishay: crcw04023r30jned c vio v io supply decoupling, 10 v 100 nf 0201 murata: grm033r61a104me15d c avdd v avdd supply decoupling, 10 v 1 f 0402 tdk: c1005x5r1a105k c vreg v vreg supply decoupling, 10 v 220 nf 0201 tdk: c0603x5r1a224m c hv boost output capacitor, 50 v 22 nf 0402 murata: grm155r71h223ka12 c daca c dacb c dacc decoupling capacitor, 50 v 100 pf 0201 murata: grm0335c1h101jd01d tcc ? 103 http://onsemi.com 27 mechanical description 2050 m 10 m tccx 7lyw pb-free (sn/ag/cu sac351) 1850 m 10 m 325 m 300 m 300 m 300 m 350 m 285 m 300 m 600 m 300 m 290 m 150 m dia 485 m 50 m 380 m figure 15. peripheral row package tcc = product code x = mipi id (see mipi version table) 7 = assembly location l = wafer lot code y = year code w = week code ? = pin 1 marker a=00 b=01 c=10 d=11 mipi version 2050 m 10 m 1850 m 10 m tccx 7lyw a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 425 m 425 m 400 m 400 m 400 m 400 m 400 m 400 m 325 m 325 m 250 m dia 580 m 380 m 25 m figure 16. ball array package pb-free (96.8% sn/2.6% ag/0.6% cu) tcc = product code x = mipi id (see mipi version table) 7 = assembly location l = wafer lot code y = year code w = week code ? = pin 1 marker a=00 b=01 c=10 d=11 mipi version tcc ? 103 http://onsemi.com 28 tape & reel dimensions figure 17. wlcsp carrier tape drawings tcc ? 103 http://onsemi.com 29 table 48. ordering information device package shipping ? tcc ? 103a ? pt peripheral bump (pb-free) 3,000 units/reel tcc ? 103a ? rt rdl (pb-free) 3,000 units/reel tcc ? 103b ? pt peripheral bump (pb-free) 3,000 units/reel tcc ? 103b ? rt rdl (pb-free) 3,000 units/reel tcc ? 103c ? pt peripheral bump (pb-free) 3,000 units/reel tcc ? 103c ? rt rdl (pb-free) 3,000 units/reel tcc ? 103d ? pt peripheral bump (pb-free) 3,000 units/reel tcc ? 103d ? rt rdl (pb-free) 3,000 units/reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 tcc ? 103/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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